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Module 03 / 04
Planned hardware path: RISC-V → SoC IP.
Capability, stability and transition supervision migrate from the software reference without changing their interfaces.
Planned hardware path: RISC-V → SoC IP.Open section
Stage 2 · planned
Planned hardware path: RISC-V → SoC IP.
SUBCORE
Move the verified kernels
Capability, stability and transition supervision migrate from the software reference without changing their interfaces.
NUMERIC
Control quantisation error
Fixed/floating-point formats are selected from sensitivity of ranking, health and stability decisions.
IP
Stable hardware boundary
Inputs: state, diagnostics and policy. Outputs: health, selected configuration, stability status and control/resource commands.
PROVE
FPGA before SoC
Numerical equivalence, cycle budgets and HIL fault scenarios must pass before SoC integration.